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tinycc/riscv64-tok.h

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riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi
2021-04-06 13:43:21 +03:00
/* ------------------------------------------------------------------ */
/* WARNING: relative order of tokens is important. */
riscv64-tok.h: update with more instructions from the spec defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
2023-08-10 14:27:11 +03:00
/*
* The specifications are available under https://riscv.org/technical/specifications/
*/
riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi
2021-04-06 13:43:21 +03:00
riscv64-asm.c: implement C extension add nop fix asm_emit_i immediate check (negative offsets were missing) fix check for IM12S remove non-existent instructions (example: slli64 is just slli with imm=0)
2023-12-03 00:46:39 +02:00
#define DEF_ASM_WITH_SUFFIX(x, y) \
DEF(TOK_ASM_ ## x ## _ ## y, #x "." #y)
riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi
2021-04-06 13:43:21 +03:00
riscv: asm: Add load-reserved and store-conditional Add Atomic instructions `ld` and `sc` in their 32 bit and 64 bit versions.
2024-04-23 13:05:05 +03:00
#define DEF_ASM_WITH_SUFFIXES(x, y, z) \
DEF(TOK_ASM_ ## x ## _ ## y ## _ ## z, #x "." #y "." #z)
riscv: Add full `fence` instruction support This commit adds support for `fence`'s predecessor and successor arguments.
2024-04-23 16:01:05 +03:00
#define DEF_ASM_FENCE(x) \
DEF(TOK_ASM_ ## x ## _fence, #x)
riscv64-asm.c: implement C extension add nop fix asm_emit_i immediate check (negative offsets were missing) fix check for IM12S remove non-existent instructions (example: slli64 is just slli with imm=0)
2023-12-03 00:46:39 +02:00
/* register */
/* integer */
riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi
2021-04-06 13:43:21 +03:00
DEF_ASM(x0)
DEF_ASM(x1)
DEF_ASM(x2)
DEF_ASM(x3)
DEF_ASM(x4)
DEF_ASM(x5)
DEF_ASM(x6)
DEF_ASM(x7)
DEF_ASM(x8)
DEF_ASM(x9)
DEF_ASM(x10)
DEF_ASM(x11)
DEF_ASM(x12)
DEF_ASM(x13)
DEF_ASM(x14)
DEF_ASM(x15)
DEF_ASM(x16)
DEF_ASM(x17)
DEF_ASM(x18)
DEF_ASM(x19)
DEF_ASM(x20)
DEF_ASM(x21)
DEF_ASM(x22)
DEF_ASM(x23)
DEF_ASM(x24)
DEF_ASM(x25)
DEF_ASM(x26)
DEF_ASM(x27)
DEF_ASM(x28)
DEF_ASM(x29)
DEF_ASM(x30)
DEF_ASM(x31)
riscv64-asm.c: implement C extension add nop fix asm_emit_i immediate check (negative offsets were missing) fix check for IM12S remove non-existent instructions (example: slli64 is just slli with imm=0)
2023-12-03 00:46:39 +02:00
/* float */
DEF_ASM(f0)
DEF_ASM(f1)
DEF_ASM(f2)
DEF_ASM(f3)
DEF_ASM(f4)
DEF_ASM(f5)
DEF_ASM(f6)
DEF_ASM(f7)
DEF_ASM(f8)
DEF_ASM(f9)
DEF_ASM(f10)
DEF_ASM(f11)
DEF_ASM(f12)
DEF_ASM(f13)
DEF_ASM(f14)
DEF_ASM(f15)
DEF_ASM(f16)
DEF_ASM(f17)
DEF_ASM(f18)
DEF_ASM(f19)
DEF_ASM(f20)
DEF_ASM(f21)
DEF_ASM(f22)
DEF_ASM(f23)
DEF_ASM(f24)
DEF_ASM(f25)
DEF_ASM(f26)
DEF_ASM(f27)
DEF_ASM(f28)
DEF_ASM(f29)
DEF_ASM(f30)
DEF_ASM(f31)
/* register ABI mnemonics, refer to RISC-V ABI 1.0 */
/* integer */
riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi
2021-04-06 13:43:21 +03:00
DEF_ASM(zero)
DEF_ASM(ra)
DEF_ASM(sp)
DEF_ASM(gp)
DEF_ASM(tp)
DEF_ASM(t0)
DEF_ASM(t1)
DEF_ASM(t2)
riscv64-asm.c: implement C extension add nop fix asm_emit_i immediate check (negative offsets were missing) fix check for IM12S remove non-existent instructions (example: slli64 is just slli with imm=0)
2023-12-03 00:46:39 +02:00
DEF_ASM(s0)
riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi
2021-04-06 13:43:21 +03:00
DEF_ASM(s1)
DEF_ASM(a0)
DEF_ASM(a1)
DEF_ASM(a2)
DEF_ASM(a3)
DEF_ASM(a4)
DEF_ASM(a5)
DEF_ASM(a6)
DEF_ASM(a7)
DEF_ASM(s2)
DEF_ASM(s3)
DEF_ASM(s4)
DEF_ASM(s5)
DEF_ASM(s6)
DEF_ASM(s7)
DEF_ASM(s8)
DEF_ASM(s9)
DEF_ASM(s10)
DEF_ASM(s11)
DEF_ASM(t3)
DEF_ASM(t4)
DEF_ASM(t5)
DEF_ASM(t6)
riscv64-asm.c: implement C extension add nop fix asm_emit_i immediate check (negative offsets were missing) fix check for IM12S remove non-existent instructions (example: slli64 is just slli with imm=0)
2023-12-03 00:46:39 +02:00
/* float */
DEF_ASM(ft0)
DEF_ASM(ft1)
DEF_ASM(ft2)
DEF_ASM(ft3)
DEF_ASM(ft4)
DEF_ASM(ft5)
DEF_ASM(ft6)
DEF_ASM(ft7)
DEF_ASM(fs0)
DEF_ASM(fs1)
DEF_ASM(fa0)
DEF_ASM(fa1)
DEF_ASM(fa2)
DEF_ASM(fa3)
DEF_ASM(fa4)
DEF_ASM(fa5)
DEF_ASM(fa6)
DEF_ASM(fa7)
DEF_ASM(fs2)
DEF_ASM(fs3)
DEF_ASM(fs4)
DEF_ASM(fs5)
DEF_ASM(fs6)
DEF_ASM(fs7)
DEF_ASM(fs8)
DEF_ASM(fs9)
DEF_ASM(fs10)
DEF_ASM(fs11)
DEF_ASM(ft8)
DEF_ASM(ft9)
DEF_ASM(ft10)
DEF_ASM(ft11)
/* not in the ABI */
riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi
2021-04-06 13:43:21 +03:00
DEF_ASM(pc)
riscv64-asm: Add lb, lh, lw, lbu, lhu, ld, lwu, sb, sh, sw, sd
2021-04-06 14:32:29 +03:00
/* Loads */
DEF_ASM(lb)
DEF_ASM(lh)
DEF_ASM(lw)
DEF_ASM(lbu)
DEF_ASM(lhu)
riscv64-tok.h: update with more instructions from the spec defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
2023-08-10 14:27:11 +03:00
/* RV64 */
riscv64-asm: Add lb, lh, lw, lbu, lhu, ld, lwu, sb, sh, sw, sd
2021-04-06 14:32:29 +03:00
DEF_ASM(ld)
DEF_ASM(lwu)
/* Stores */
DEF_ASM(sb)
DEF_ASM(sh)
DEF_ASM(sw)
riscv64-tok.h: update with more instructions from the spec defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
2023-08-10 14:27:11 +03:00
/* RV64 */
riscv64-asm: Add lb, lh, lw, lbu, lhu, ld, lwu, sb, sh, sw, sd
2021-04-06 14:32:29 +03:00
DEF_ASM(sd)
riscv64-asm: Add sll, slli, srl, srli, sra, srai, sllw, slld, slliw, sllid, srlw, srld, srliw, srlid, sraw, srad, sraiw, sraid
2021-04-06 14:22:08 +03:00
/* Shifts */
DEF_ASM(sll)
DEF_ASM(srl)
DEF_ASM(sra)
riscv64-tok.h: update with more instructions from the spec defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
2023-08-10 14:27:11 +03:00
/* RV64 */
DEF_ASM(slli)
DEF_ASM(srli)
riscv64-asm: Add sll, slli, srl, srli, sra, srai, sllw, slld, slliw, sllid, srlw, srld, srliw, srlid, sraw, srad, sraiw, sraid
2021-04-06 14:22:08 +03:00
DEF_ASM(sllw)
DEF_ASM(slliw)
DEF_ASM(srlw)
DEF_ASM(srliw)
riscv64-tok.h: update with more instructions from the spec defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
2023-08-10 14:27:11 +03:00
DEF_ASM(srai)
riscv64-asm: Add sll, slli, srl, srli, sra, srai, sllw, slld, slliw, sllid, srlw, srld, srliw, srlid, sraw, srad, sraiw, sraid
2021-04-06 14:22:08 +03:00
DEF_ASM(sraw)
DEF_ASM(sraiw)
riscv64-asm: Add lui, auipc
2021-04-06 14:13:52 +03:00
/* Arithmetic */
riscv64-asm: Add add, addi, sub, addw, addd, addiw, addid, subw, subd, xor, xori, or, ori, and, andi, slt, slti, sltu, sltiu
2021-04-06 14:26:09 +03:00
DEF_ASM(add)
DEF_ASM(addi)
DEF_ASM(sub)
riscv64-asm: Add lui, auipc
2021-04-06 14:13:52 +03:00
DEF_ASM(lui)
DEF_ASM(auipc)
riscv64-tok.h: update with more instructions from the spec defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
2023-08-10 14:27:11 +03:00
/* RV64 */
riscv64-asm: Add add, addi, sub, addw, addd, addiw, addid, subw, subd, xor, xori, or, ori, and, andi, slt, slti, sltu, sltiu
2021-04-06 14:26:09 +03:00
DEF_ASM(addw)
DEF_ASM(addiw)
DEF_ASM(subw)
/* Logical */
DEF_ASM(xor)
DEF_ASM(xori)
DEF_ASM(or)
DEF_ASM(ori)
DEF_ASM(and)
DEF_ASM(andi)
/* Compare */
DEF_ASM(slt)
DEF_ASM(slti)
DEF_ASM(sltu)
DEF_ASM(sltiu)
riscv64-asm: Add beq, bne, blt, bge, bltu, bgeu
2021-04-06 14:36:33 +03:00
/* Branch */
DEF_ASM(beq)
DEF_ASM(bne)
DEF_ASM(blt)
DEF_ASM(bge)
DEF_ASM(bltu)
DEF_ASM(bgeu)
riscv64-tok.h: update with more instructions from the spec defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
2023-08-10 14:27:11 +03:00
/* Jump */
DEF_ASM(jal)
DEF_ASM(jalr)
riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi
2021-04-06 13:43:21 +03:00
/* Sync */
DEF_ASM(fence)
riscv64-tok.h: update with more instructions from the spec defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
2023-08-10 14:27:11 +03:00
/* Zifencei extension */
riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi
2021-04-06 13:43:21 +03:00
DEF_ASM_WITH_SUFFIX(fence, i)
/* System call */
riscv64-tok.h: update with more instructions from the spec defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
2023-08-10 14:27:11 +03:00
/* used to be called scall and sbreak */
DEF_ASM(ecall)
DEF_ASM(ebreak)
riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi
2021-04-06 13:43:21 +03:00
riscv64-asm: Add rdcycle, rdcycleh, rdtime, rdtimeh, rdinstret, rdinstreth
2021-04-06 13:51:18 +03:00
/* Counters */
DEF_ASM(rdcycle)
DEF_ASM(rdcycleh)
DEF_ASM(rdtime)
DEF_ASM(rdtimeh)
DEF_ASM(rdinstret)
DEF_ASM(rdinstreth)
riscv64-tok.h: update with more instructions from the spec defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
2023-08-10 14:27:11 +03:00
/* “M” Standard Extension for Integer Multiplication and Division, V2.0 */
DEF_ASM(mul)
DEF_ASM(mulh)
DEF_ASM(mulhsu)
DEF_ASM(mulhu)
DEF_ASM(div)
DEF_ASM(divu)
DEF_ASM(rem)
DEF_ASM(remu)
/* RV64 */
DEF_ASM(mulw)
DEF_ASM(divw)
DEF_ASM(divuw)
DEF_ASM(remw)
DEF_ASM(remuw)
/* "C" Extension for Compressed Instructions, V2.0 */
riscv64-asm.c: add support for calculating addresses of symbols add some pseudoinstructions riscv64-tok.h: add pseudoinstructions from tables 25.{2,3}
2023-12-10 23:36:49 +02:00
DEF_ASM_WITH_SUFFIX(c, nop)
riscv64-tok.h: update with more instructions from the spec defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
2023-08-10 14:27:11 +03:00
/* Loads */
DEF_ASM_WITH_SUFFIX(c, li)
DEF_ASM_WITH_SUFFIX(c, lw)
DEF_ASM_WITH_SUFFIX(c, lwsp)
/* single float */
DEF_ASM_WITH_SUFFIX(c, flw)
DEF_ASM_WITH_SUFFIX(c, flwsp)
/* double float */
DEF_ASM_WITH_SUFFIX(c, fld)
DEF_ASM_WITH_SUFFIX(c, fldsp)
/* RV64 */
DEF_ASM_WITH_SUFFIX(c, ld)
DEF_ASM_WITH_SUFFIX(c, ldsp)
riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi
2021-04-06 13:43:21 +03:00
riscv64-tok.h: update with more instructions from the spec defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
2023-08-10 14:27:11 +03:00
/* Stores */
DEF_ASM_WITH_SUFFIX(c, sw)
DEF_ASM_WITH_SUFFIX(c, sd)
DEF_ASM_WITH_SUFFIX(c, swsp)
DEF_ASM_WITH_SUFFIX(c, sdsp)
/* single float */
DEF_ASM_WITH_SUFFIX(c, fsw)
DEF_ASM_WITH_SUFFIX(c, fswsp)
/* double float */
DEF_ASM_WITH_SUFFIX(c, fsd)
DEF_ASM_WITH_SUFFIX(c, fsdsp)
/* Shifts */
DEF_ASM_WITH_SUFFIX(c, slli)
DEF_ASM_WITH_SUFFIX(c, srli)
DEF_ASM_WITH_SUFFIX(c, srai)
/* Arithmetic */
DEF_ASM_WITH_SUFFIX(c, add)
DEF_ASM_WITH_SUFFIX(c, addi)
DEF_ASM_WITH_SUFFIX(c, addi16sp)
DEF_ASM_WITH_SUFFIX(c, addi4spn)
DEF_ASM_WITH_SUFFIX(c, lui)
DEF_ASM_WITH_SUFFIX(c, sub)
DEF_ASM_WITH_SUFFIX(c, mv)
/* RV64 */
DEF_ASM_WITH_SUFFIX(c, addw)
DEF_ASM_WITH_SUFFIX(c, addiw)
DEF_ASM_WITH_SUFFIX(c, subw)
/* Logical */
DEF_ASM_WITH_SUFFIX(c, xor)
DEF_ASM_WITH_SUFFIX(c, or)
DEF_ASM_WITH_SUFFIX(c, and)
DEF_ASM_WITH_SUFFIX(c, andi)
/* Branch */
DEF_ASM_WITH_SUFFIX(c, beqz)
DEF_ASM_WITH_SUFFIX(c, bnez)
/* Jump */
DEF_ASM_WITH_SUFFIX(c, j)
DEF_ASM_WITH_SUFFIX(c, jr)
DEF_ASM_WITH_SUFFIX(c, jal)
DEF_ASM_WITH_SUFFIX(c, jalr)
/* System call */
DEF_ASM_WITH_SUFFIX(c, ebreak)
/* XXX F Extension: Single-Precision Floating Point */
/* XXX D Extension: Double-Precision Floating Point */
/* from the spec: Tables 16.5–16.7 list the RVC instructions. */
/* “Zicsr”, Control and Status Register (CSR) Instructions, V2.0 */
DEF_ASM(csrrw)
DEF_ASM(csrrs)
DEF_ASM(csrrc)
DEF_ASM(csrrwi)
DEF_ASM(csrrsi)
DEF_ASM(csrrci)
riscv64-tok.h: add Zicsr pseudoinstructions, registers
2023-12-10 16:22:41 +02:00
/* registers */
DEF_ASM(cycle)
DEF_ASM(fcsr)
DEF_ASM(fflags)
DEF_ASM(frm)
DEF_ASM(instret)
DEF_ASM(time)
/* RV32I-only */
DEF_ASM(cycleh)
DEF_ASM(instreth)
DEF_ASM(timeh)
/* pseudo */
DEF_ASM(csrc)
DEF_ASM(csrci)
DEF_ASM(csrr)
DEF_ASM(csrs)
DEF_ASM(csrsi)
DEF_ASM(csrw)
DEF_ASM(csrwi)
DEF_ASM(frcsr)
riscv64-asm.c: add support for calculating addresses of symbols add some pseudoinstructions riscv64-tok.h: add pseudoinstructions from tables 25.{2,3}
2023-12-10 23:36:49 +02:00
DEF_ASM(frflags)
riscv64-tok.h: add Zicsr pseudoinstructions, registers
2023-12-10 16:22:41 +02:00
DEF_ASM(frrm)
DEF_ASM(fscsr)
riscv64-asm.c: add support for calculating addresses of symbols add some pseudoinstructions riscv64-tok.h: add pseudoinstructions from tables 25.{2,3}
2023-12-10 23:36:49 +02:00
DEF_ASM(fsflags)
riscv64-tok.h: add Zicsr pseudoinstructions, registers
2023-12-10 16:22:41 +02:00
DEF_ASM(fsrm)
riscv64-tok.h: update with more instructions from the spec defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
2023-08-10 14:27:11 +03:00
/* Privileged Instructions */
riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi
2021-04-06 13:43:21 +03:00
DEF_ASM(mrts)
DEF_ASM(mrth)
DEF_ASM(hrts)
DEF_ASM(wfi)
riscv64-asm.c: add support for calculating addresses of symbols add some pseudoinstructions riscv64-tok.h: add pseudoinstructions from tables 25.{2,3}
2023-12-10 23:36:49 +02:00
/* pseudoinstructions */
DEF_ASM(beqz)
DEF_ASM(bgez)
DEF_ASM(bgt)
DEF_ASM(bgtu)
DEF_ASM(bgtz)
DEF_ASM(ble)
DEF_ASM(bleu)
DEF_ASM(blez)
DEF_ASM(bltz)
DEF_ASM(bnez)
DEF_ASM(call)
DEF_ASM_WITH_SUFFIX(fabs, d)
DEF_ASM_WITH_SUFFIX(fabs, s)
DEF_ASM(fld)
DEF_ASM(flw)
DEF_ASM_WITH_SUFFIX(fmv, d)
DEF_ASM_WITH_SUFFIX(fmv, s)
DEF_ASM_WITH_SUFFIX(fneg, d)
DEF_ASM_WITH_SUFFIX(fneg, s)
DEF_ASM(fsd)
DEF_ASM(fsw)
DEF_ASM(j)
riscv: Add pseudoinstructions call, tail, jump, jr, mv, not, neg, negw, seqz, snez, sltz, sgtz, bnez, beqz, blez, bgez, bltz, bgtz, li
2024-03-20 00:27:58 +02:00
DEF_ASM(jump)
DEF_ASM(jr)
riscv64-asm.c: add support for calculating addresses of symbols add some pseudoinstructions riscv64-tok.h: add pseudoinstructions from tables 25.{2,3}
2023-12-10 23:36:49 +02:00
DEF_ASM(la)
DEF_ASM(li)
DEF_ASM(lla)
DEF_ASM(mv)
DEF_ASM(neg)
DEF_ASM(negw)
DEF_ASM(nop)
DEF_ASM(not)
DEF_ASM(ret)
DEF_ASM(seqz)
DEF_ASM_WITH_SUFFIX(sext, w)
DEF_ASM(sgtz)
DEF_ASM(sltz)
DEF_ASM(snez)
DEF_ASM(tail)
riscv: Add .option assembly directive (unimp)
2024-03-20 18:53:41 +02:00
/* Possible values for .option directive */
DEF_ASM(arch)
DEF_ASM(rvc)
DEF_ASM(norvc)
DEF_ASM(pic)
DEF_ASM(nopic)
DEF_ASM(relax)
DEF_ASM(norelax)
DEF_ASM(push)
DEF_ASM(pop)
riscv: asm: Add load-reserved and store-conditional Add Atomic instructions `ld` and `sc` in their 32 bit and 64 bit versions.
2024-04-23 13:05:05 +03:00
/* “A” Standard Extension for Atomic Instructions, Version 2.1 */
/* XXX: Atomic memory operations */
DEF_ASM_WITH_SUFFIX(lr, w)
DEF_ASM_WITH_SUFFIXES(lr, w, aq)
DEF_ASM_WITH_SUFFIXES(lr, w, rl)
DEF_ASM_WITH_SUFFIXES(lr, w, aqrl)
DEF_ASM_WITH_SUFFIX(lr, d)
DEF_ASM_WITH_SUFFIXES(lr, d, aq)
DEF_ASM_WITH_SUFFIXES(lr, d, rl)
DEF_ASM_WITH_SUFFIXES(lr, d, aqrl)
DEF_ASM_WITH_SUFFIX(sc, w)
DEF_ASM_WITH_SUFFIXES(sc, w, aq)
DEF_ASM_WITH_SUFFIXES(sc, w, rl)
DEF_ASM_WITH_SUFFIXES(sc, w, aqrl)
DEF_ASM_WITH_SUFFIX(sc, d)
DEF_ASM_WITH_SUFFIXES(sc, d, aq)
DEF_ASM_WITH_SUFFIXES(sc, d, rl)
DEF_ASM_WITH_SUFFIXES(sc, d, aqrl)
riscv: Add full `fence` instruction support This commit adds support for `fence`'s predecessor and successor arguments.
2024-04-23 16:01:05 +03:00
/* `fence` arguments */
/* NOTE: Order is important */
DEF_ASM_FENCE(w)
DEF_ASM_FENCE(r)
DEF_ASM_FENCE(rw)
DEF_ASM_FENCE(o)
DEF_ASM_FENCE(ow)
DEF_ASM_FENCE(or)
DEF_ASM_FENCE(orw)
DEF_ASM_FENCE(i)
DEF_ASM_FENCE(iw)
DEF_ASM_FENCE(ir)
DEF_ASM_FENCE(irw)
DEF_ASM_FENCE(io)
DEF_ASM_FENCE(iow)
DEF_ASM_FENCE(ior)
DEF_ASM_FENCE(iorw)
riscv64-asm.c: implement C extension add nop fix asm_emit_i immediate check (negative offsets were missing) fix check for IM12S remove non-existent instructions (example: slli64 is just slli with imm=0)
2023-12-03 00:46:39 +02:00
#undef DEF_ASM_WITH_SUFFIX