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riscv64-asm.c: implement C extension 

add nop
fix asm_emit_i immediate check (negative offsets were missing)
fix check for IM12S
remove non-existent instructions (example: slli64 is just slli with imm=0)
This commit is contained in:
noneofyourbusiness 2023-12-02 23:46:39 +01:00
parent 81a32ec305
commit d87801bd50
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2 changed files with 888 additions and 246 deletions
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1040
riscv64-asm.c
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File diff suppressed because it is too large Load Diff

94
riscv64-tok.h
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@ -5,8 +5,11 @@
* The specifications are available under https://riscv.org/technical/specifications/
*/
/* register */
#define DEF_ASM_WITH_SUFFIX(x, y) \
DEF(TOK_ASM_ ## x ## _ ## y, #x "." #y)
/* register */
/* integer */
DEF_ASM(x0)
DEF_ASM(x1)
DEF_ASM(x2)
@ -39,9 +42,42 @@
DEF_ASM(x29)
DEF_ASM(x30)
DEF_ASM(x31)
/* float */
DEF_ASM(f0)
DEF_ASM(f1)
DEF_ASM(f2)
DEF_ASM(f3)
DEF_ASM(f4)
DEF_ASM(f5)
DEF_ASM(f6)
DEF_ASM(f7)
DEF_ASM(f8)
DEF_ASM(f9)
DEF_ASM(f10)
DEF_ASM(f11)
DEF_ASM(f12)
DEF_ASM(f13)
DEF_ASM(f14)
DEF_ASM(f15)
DEF_ASM(f16)
DEF_ASM(f17)
DEF_ASM(f18)
DEF_ASM(f19)
DEF_ASM(f20)
DEF_ASM(f21)
DEF_ASM(f22)
DEF_ASM(f23)
DEF_ASM(f24)
DEF_ASM(f25)
DEF_ASM(f26)
DEF_ASM(f27)
DEF_ASM(f28)
DEF_ASM(f29)
DEF_ASM(f30)
DEF_ASM(f31)
/* register macros */
/* register ABI mnemonics, refer to RISC-V ABI 1.0 */
/* integer */
DEF_ASM(zero)
DEF_ASM(ra)
DEF_ASM(sp)
@ -50,7 +86,7 @@
DEF_ASM(t0)
DEF_ASM(t1)
DEF_ASM(t2)
DEF_ASM(fp)
DEF_ASM(s0)
DEF_ASM(s1)
DEF_ASM(a0)
DEF_ASM(a1)
@ -74,14 +110,42 @@
DEF_ASM(t4)
DEF_ASM(t5)
DEF_ASM(t6)
DEF_ASM(s0) // = x8
/* float */
DEF_ASM(ft0)
DEF_ASM(ft1)
DEF_ASM(ft2)
DEF_ASM(ft3)
DEF_ASM(ft4)
DEF_ASM(ft5)
DEF_ASM(ft6)
DEF_ASM(ft7)
DEF_ASM(fs0)
DEF_ASM(fs1)
DEF_ASM(fa0)
DEF_ASM(fa1)
DEF_ASM(fa2)
DEF_ASM(fa3)
DEF_ASM(fa4)
DEF_ASM(fa5)
DEF_ASM(fa6)
DEF_ASM(fa7)
DEF_ASM(fs2)
DEF_ASM(fs3)
DEF_ASM(fs4)
DEF_ASM(fs5)
DEF_ASM(fs6)
DEF_ASM(fs7)
DEF_ASM(fs8)
DEF_ASM(fs9)
DEF_ASM(fs10)
DEF_ASM(fs11)
DEF_ASM(ft8)
DEF_ASM(ft9)
DEF_ASM(ft10)
DEF_ASM(ft11)
/* not in the ABI */
DEF_ASM(pc)
#define DEF_ASM_WITH_SUFFIX(x, y) \
DEF(TOK_ASM_ ## x ## _ ## y, #x #y)
/* Loads */
DEF_ASM(lb)
@ -110,18 +174,12 @@
DEF_ASM(slli)
DEF_ASM(srli)
DEF_ASM(sllw)
DEF_ASM(slld)
DEF_ASM(slliw)
DEF_ASM(sllid)
DEF_ASM(srlw)
DEF_ASM(srld)
DEF_ASM(srliw)
DEF_ASM(srlid)
DEF_ASM(srai)
DEF_ASM(sraw)
DEF_ASM(srad)
DEF_ASM(sraiw)
DEF_ASM(sraid)
/* Arithmetic */
@ -236,11 +294,8 @@
/* Shifts */
DEF_ASM_WITH_SUFFIX(c, slli)
DEF_ASM_WITH_SUFFIX(c, slli64)
DEF_ASM_WITH_SUFFIX(c, srli)
DEF_ASM_WITH_SUFFIX(c, srli64)
DEF_ASM_WITH_SUFFIX(c, srai)
DEF_ASM_WITH_SUFFIX(c, srai64)
/* Arithmetic */
DEF_ASM_WITH_SUFFIX(c, add)
@ -293,3 +348,4 @@
DEF_ASM(hrts)
DEF_ASM(wfi)
#undef DEF_ASM_WITH_SUFFIX