riscv: Add .option assembly directive (unimp)

Needed for using `__global_pointer$`.
$ don't have special meaning in RISC-V assembly.

lib/libtcc1.c

@@ -107,7 +107,7 @@ union float_long {
 };
 
 /* XXX: we don't support several builtin supports for now */
-#if !defined __x86_64__ && !defined __arm__
+#if !defined __x86_64__ && !defined __arm__ && !defined __riscv
 
 /* XXX: use gcc/tcc intrinsic ? */
 #if defined __i386__

riscv64-asm.c

@@ -152,6 +152,12 @@ static void asm_nullary_opcode(TCCState *s1, int token)
         asm_emit_opcode((0x1C << 2) | 3 | (0x105 << 20));
         return;
 
+    /* Pseudoinstructions */
+    case TOK_ASM_ret:
+        /* jalr zero, x1, 0 */
+        asm_emit_opcode( 0x67 | (0 << 12) | ENCODE_RS1(1) );
+        return;
+
     /* C extension */
     case TOK_ASM_c_ebreak:
         asm_emit_cr(token, 2 | (9 << 12), &nil, &nil);
@@ -261,11 +267,80 @@ static void parse_mem_access_operands(TCCState *s1, Operand* ops){
     }
 }
 
+/* This is special: First operand is optional */
+static void asm_jal_opcode(TCCState *s1, int token){
+    static const Operand ra = {.type = OP_REG, .reg = 1};
+    Operand ops[2];
+    parse_operand(s1, &ops[0]);
+    if ( tok == ',')
+        next();
+    else {
+        /* no more operands, it's the pseudoinstruction:
+         *  jal rs
+         * Expand to:
+         *  jal ra, rs
+         */
+        asm_emit_j(token, 0x6f, &ra, &ops[0]);
+        return;
+    }
+    parse_operand(s1, &ops[1]);
+    asm_emit_j(token, 0x6f, &ops[0], &ops[1]);
+}
+
+/* This is special: It can be a pseudointruction or a instruction */
+static void asm_jalr_opcode(TCCState *s1, int token){
+    static const Operand zimm = {.type = OP_IM12S};
+    static const Operand ra = {.type = OP_REG, .reg = 1};
+    Operand ops[3];
+    Operand op;
+    int i;
+
+    parse_operand(s1, &ops[0]);
+    if ( tok == ',')
+        next();
+    else {
+        /* no more operands, it's the pseudoinstruction:
+         *  jalr rs
+         * Expand to:
+         *  jalr ra, 0(rs)
+         */
+        asm_emit_i(token, 0x67 | (0 << 12), &ra, &ops[0], &zimm);
+        return;
+    }
+
+    if ( tok == '(') {
+        /* `X, (Y)` case*/
+        next();
+        parse_operand(s1, &ops[1]);
+        if ( tok == ')') next(); else expect("')'");
+        ops[2] = zimm;
+    } else {
+        parse_operand(s1, &ops[2]);
+        if ( tok == '('){
+            /* `X, imm(Y)` case*/
+            next();
+            parse_operand(s1, &ops[1]);
+            if ( tok == ')') next(); else expect("')'");
+        } else {
+            /* `X, Y` case*/
+            /* we parsed Y thinking it was imm, swap and default imm to zero */
+            op = ops[2];
+            ops[1] = ops[2];
+            ops[2] = op;
+            ops[2] = zimm;
+        }
+    }
+    /* jalr(RD, RS1, IMM); I-format */
+    asm_emit_i(token, 0x67 | (0 << 12), &ops[0], &ops[1], &ops[2]);
+}
+
+
 static void asm_unary_opcode(TCCState *s1, int token)
 {
     uint32_t opcode = (0x1C << 2) | 3 | (2 << 12);
     Operand op;
-    static const Operand nil = {.type = OP_REG};
+    static const Operand zero = {.type = OP_REG};
+    static const Operand zimm = {.type = OP_IM12S};
 
     parse_operands(s1, &op, 1);
     /* Note: Those all map to CSR--so they are pseudo-instructions. */
@@ -291,6 +366,26 @@ static void asm_unary_opcode(TCCState *s1, int token)
     case TOK_ASM_rdinstreth:
         asm_emit_opcode(opcode | (0xC82 << 20) | ENCODE_RD(op.reg));
         return;
+
+    case TOK_ASM_jr:
+        /* jalr zero, 0(rs)*/
+        asm_emit_i(token, 0x67 | (0 << 12), &zero, &op, &zimm);
+        return;
+    case TOK_ASM_call:
+        /* auipc ra, 0 */
+        greloca(cur_text_section, op.e.sym, ind, R_RISCV_CALL, 0);
+        asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(1));
+        /* jalr zero, 0(ra) */
+        asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(1));
+        return;
+    case TOK_ASM_tail:
+        /* auipc x6, 0 */
+        greloca(cur_text_section, op.e.sym, ind, R_RISCV_CALL, 0);
+        asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(6));
+        /* jalr zero, 0(x6) */
+        asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(6));
+        return;
+
     /* C extension */
     case TOK_ASM_c_j:
         asm_emit_cj(token, 1 | (5 << 13), &op);
@@ -299,10 +394,10 @@ static void asm_unary_opcode(TCCState *s1, int token)
         asm_emit_cj(token, 1 | (1 << 13), &op);
         return;
     case TOK_ASM_c_jalr:
-        asm_emit_cr(token, 2 | (9 << 12), &op, &nil);
+        asm_emit_cr(token, 2 | (9 << 12), &op, &zero);
         return;
     case TOK_ASM_c_jr:
-        asm_emit_cr(token, 2 | (8 << 12), &op, &nil);
+        asm_emit_cr(token, 2 | (8 << 12), &op, &zero);
         return;
     default:
         expect("unary instruction");
@@ -331,6 +426,8 @@ static void asm_emit_u(int token, uint32_t opcode, const Operand* rd, const Oper
 
 static void asm_binary_opcode(TCCState* s1, int token)
 {
+    static const Operand zero = {.type = OP_REG, .reg = 0};
+    Operand imm = {.type = OP_IM12S, .e = {.v = 0}};
     Operand ops[2];
     parse_operands(s1, &ops[0], 2);
 
@@ -341,9 +438,6 @@ static void asm_binary_opcode(TCCState* s1, int token)
     case TOK_ASM_auipc:
         asm_emit_u(token, (0x05 << 2) | 3, &ops[0], &ops[1]);
         return;
-    case TOK_ASM_jal:
-        asm_emit_j(token, 0x6f, ops, ops + 1);
-        return;
 
     /* C extension */
     case TOK_ASM_c_add:
@@ -452,6 +546,110 @@ static void asm_binary_opcode(TCCState* s1, int token)
         /* addi rd, rd, 0 */
         asm_emit_i(token, 3 | (4 << 2), ops, ops, ops + 1);
         return;
+    case TOK_ASM_li:
+        if(ops[1].type != OP_IM32 && ops[1].type != OP_IM12S){
+            tcc_error("'%s': Expected first source operand that is an immediate value between 0 and 0xFFFFFFFFFFFFFFFF", get_tok_str(token, NULL));
+        }
+        int32_t lo = ops[1].e.v;
+        uint32_t hi = (int64_t)ops[1].e.v >> 32;
+        if(lo < 0){
+            hi += 1;
+        }
+        imm.e.v = ((hi + 0x800) & 0xfffff000) >> 12;
+        /* lui rd, HI_20(HI_32(imm)) */
+        asm_emit_u(token, (0xD << 2) | 3, &ops[0], &imm);
+        /* addi rd, rd, LO_12(HI_32(imm)) */
+        imm.e.v = (int32_t)hi<<20>>20;
+        asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[0], &imm);
+        /* slli rd, rd, 12 */
+        imm.e.v = 12;
+        asm_emit_i(token, (4 << 2) | 3 | (1 << 12), &ops[0], &ops[0], &imm);
+        /* addi rd, rd, HI_12(LO_32(imm)) */
+        imm.e.v = (lo + (1<<19)) >> 20;
+        asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[0], &imm);
+        /* slli rd, rd, 12 */
+        imm.e.v = 12;
+        asm_emit_i(token, (4 << 2) | 3 | (1 << 12), &ops[0], &ops[0], &imm);
+        /* addi rd, rd, HI_12(LO_20(LO_32imm)) */
+        lo = lo << 12 >> 12;
+        imm.e.v = lo >> 8;
+        asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[0], &imm);
+        /* slli rd, rd,  8 */
+        imm.e.v = 8;
+        asm_emit_i(token, (4 << 2) | 3 | (1 << 12), &ops[0], &ops[0], &imm);
+        /* addi rd, rd, LO_8(LO_20(LO_32imm)) */
+        lo &= 0xff;
+        imm.e.v = lo << 20 >> 20;
+        asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[0], &imm);
+        return;
+    case TOK_ASM_mv:
+        /* addi rd, rs, 0 */
+        asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[1], &imm);
+        return;
+    case TOK_ASM_not:
+        /* xori rd, rs, -1 */
+        imm.e.v = -1;
+        asm_emit_i(token, (0x4 << 2) | 3 | (4 << 12), &ops[0], &ops[1], &imm);
+        return;
+    case TOK_ASM_neg:
+        /* sub rd, x0, rs */
+        imm.e.v = 1;
+        asm_emit_i(token, (0x4 << 2) | 3 | (4 << 12), &ops[0], &zero, &imm);
+        return;
+    case TOK_ASM_negw:
+        /* sub rd, x0, rs */
+        imm.e.v = 1;
+        asm_emit_i(token, (0x4 << 2) | 3 | (4 << 12), &ops[0], &zero, &imm);
+        return;
+    case TOK_ASM_jump:
+        /* auipc x5, 0 */
+        asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(5));
+        greloca(cur_text_section, ops->e.sym, ind, R_RISCV_CALL, 0);
+        /* jalr zero, 0(x5) */
+        asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(5));
+        return;
+    case TOK_ASM_seqz:
+        /* sltiu rd, rs, 1 */
+        imm.e.v = 1;
+        asm_emit_i(token, (0x4 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &imm);
+        return;
+    case TOK_ASM_snez:
+        /* sltu rd, zero, rs */
+        imm.e.v = 1;
+        asm_emit_r(token, (0xC << 2) | 3 | (3 << 12), &ops[0], &zero, &ops[1]);
+        return;
+    case TOK_ASM_sltz:
+        /* slt rd, rs, zero */
+        asm_emit_r(token, (0xC << 2) | 3 | (2 << 12), &ops[0], &ops[1], &zero);
+        return;
+    case TOK_ASM_sgtz:
+        /* slt rd, zero, rs */
+        asm_emit_r(token, (0xC << 2) | 3 | (2 << 12), &ops[0], &zero, &ops[1]);
+        return;
+    case TOK_ASM_bnez:
+        /* bne rs, zero, offset */
+        asm_emit_b(token, 0x63 | (1 << 12), &ops[0], &zero, &ops[1]);
+        return;
+    case TOK_ASM_beqz:
+        /* bne rs, zero, offset */
+        asm_emit_b(token, 0x63 | (0 << 12), &ops[0], &zero, &ops[1]);
+        return;
+    case TOK_ASM_blez:
+        /* bge rs, zero, offset */
+        asm_emit_b(token, 0x63 | (5 << 12), &ops[0], &zero, &ops[1]);
+        return;
+    case TOK_ASM_bgez:
+        /* bge zero, rs, offset */
+        asm_emit_b(token, 0x63 | (5 << 12), &zero, &ops[0], &ops[1]);
+        return;
+    case TOK_ASM_bltz:
+        /* blt rs, zero, offset */
+        asm_emit_b(token, 0x63 | (4 << 12), &ops[0], &zero, &ops[1]);
+        return;
+    case TOK_ASM_bgtz:
+        /* blt zero, rs, offset */
+        asm_emit_b(token, 0x63 | (4 << 12), &zero, &ops[0], &ops[1]);
+        return;
 
     default:
         expect("binary instruction");
@@ -549,8 +747,23 @@ static void asm_mem_access_opcode(TCCState *s1, int token)
     Operand ops[3];
     parse_mem_access_operands(s1, &ops[0]);
 
-    // l{b|h|w|d}[u] rd, imm(rs1); I-format
+    /* Pseudoinstruction: inst reg, label
+     * expand to:
+     *   auipc reg, 0
+     *   inst reg, 0(reg)
+     * And with the proper relocation to label
+     */
+    if (ops[1].type == OP_IM32 && ops[1].e.sym && ops[1].e.sym->type.t & VT_STATIC){
+        ops[1] = ops[0];
+        /* set the offset to zero */
+        ops[2].type = OP_IM12S;
+        ops[2].e.v  = 0;
+        /* auipc reg, 0 */
+        asm_emit_u(token, (0x05 << 2) | 3, &ops[0], &ops[2]);
+    }
+
     switch (token) {
+    // l{b|h|w|d}[u] rd, imm(rs1); I-format
     case TOK_ASM_lb:
          asm_emit_i(token, (0x0 << 2) | 3, &ops[0], &ops[1], &ops[2]);
          return;
@@ -689,11 +902,6 @@ static void asm_ternary_opcode(TCCState *s1, int token)
          asm_emit_i(token, (0x4 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]);
          return;
 
-    /* indirect jump (RD, RS1, IMM); I-format */
-    case TOK_ASM_jalr:
-        asm_emit_i(token, 0x67 | (0 << 12), ops, ops + 1, ops + 2);
-        return;
-
     /* branch (RS1, RS2, IMM); B-format */
     case TOK_ASM_beq:
         asm_emit_b(token, 0x63 | (0 << 12), ops, ops + 1, ops + 2);
@@ -713,6 +921,19 @@ static void asm_ternary_opcode(TCCState *s1, int token)
     case TOK_ASM_bgeu:
         asm_emit_b(token, 0x63 | (7 << 12), ops, ops + 1, ops + 2);
         return;
+    /* related pseudoinstructions */
+    case TOK_ASM_bgt:
+        asm_emit_b(token, 0x63 | (4 << 12), ops + 1, ops, ops + 2);
+        return;
+    case TOK_ASM_ble:
+        asm_emit_b(token, 0x63 | (5 << 12), ops + 1, ops, ops + 2);
+        return;
+    case TOK_ASM_bgtu:
+        asm_emit_b(token, 0x63 | (6 << 12), ops + 1, ops, ops + 2);
+        return;
+    case TOK_ASM_bleu:
+        asm_emit_b(token, 0x63 | (7 << 12), ops + 1, ops, ops + 2);
+        return;
 
     /* M extension */
     case TOK_ASM_div:
@@ -896,7 +1117,6 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
 
     case TOK_ASM_lui:
     case TOK_ASM_auipc:
-    case TOK_ASM_jal:
         asm_binary_opcode(s1, token);
         return;
 
@@ -914,6 +1134,13 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
         asm_mem_access_opcode(s1, token);
         break;
 
+    case TOK_ASM_jalr:
+        asm_jalr_opcode(s1, token); /* it can be a pseudo instruction too*/
+        break;
+    case TOK_ASM_jal:
+        asm_jal_opcode(s1, token); /* it can be a pseudo instruction too*/
+        break;
+
     case TOK_ASM_add:
     case TOK_ASM_addi:
     case TOK_ASM_addiw:
@@ -926,7 +1153,6 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
     case TOK_ASM_blt:
     case TOK_ASM_bltu:
     case TOK_ASM_bne:
-    case TOK_ASM_jalr:
     case TOK_ASM_or:
     case TOK_ASM_ori:
     case TOK_ASM_sll:
@@ -1030,14 +1256,44 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
 
     /* pseudoinstructions */
     case TOK_ASM_nop:
+    case TOK_ASM_ret:
         asm_nullary_opcode(s1, token);
         return;
 
+    case TOK_ASM_jr:
+    case TOK_ASM_call:
+    case TOK_ASM_tail:
+        asm_unary_opcode(s1, token);
+        return;
+
     case TOK_ASM_la:
     case TOK_ASM_lla:
+    case TOK_ASM_li:
+    case TOK_ASM_jump:
+    case TOK_ASM_seqz:
+    case TOK_ASM_snez:
+    case TOK_ASM_sltz:
+    case TOK_ASM_sgtz:
+    case TOK_ASM_bnez:
+    case TOK_ASM_beqz:
+    case TOK_ASM_blez:
+    case TOK_ASM_bgez:
+    case TOK_ASM_bltz:
+    case TOK_ASM_bgtz:
+    case TOK_ASM_mv:
+    case TOK_ASM_not:
+    case TOK_ASM_neg:
+    case TOK_ASM_negw:
         asm_binary_opcode(s1, token);
         return;
 
+    case TOK_ASM_bgt:
+    case TOK_ASM_bgtu:
+    case TOK_ASM_ble:
+    case TOK_ASM_bleu:
+        asm_ternary_opcode(s1, token);
+        return;
+
     default:
         expect("known instruction");
     }

riscv64-tok.h

@@ -393,6 +393,8 @@
  DEF_ASM(fsd)
  DEF_ASM(fsw)
  DEF_ASM(j)
+ DEF_ASM(jump)
+ DEF_ASM(jr)
  DEF_ASM(la)
  DEF_ASM(li)
  DEF_ASM(lla)
@@ -409,4 +411,15 @@
  DEF_ASM(snez)
  DEF_ASM(tail)
 
+/* Possible values for .option directive */
+ DEF_ASM(arch)
+ DEF_ASM(rvc)
+ DEF_ASM(norvc)
+ DEF_ASM(pic)
+ DEF_ASM(nopic)
+ DEF_ASM(relax)
+ DEF_ASM(norelax)
+ DEF_ASM(push)
+ DEF_ASM(pop)
+
 #undef DEF_ASM_WITH_SUFFIX

tccasm.c

@@ -922,6 +922,29 @@ static void asm_parse_directive(TCCState *s1, int global)
     case TOK_ASMDIR_code64:
         next();
         break;
+#endif
+#ifdef TCC_TARGET_RISCV64
+    case TOK_ASMDIR_option:
+        next();
+        switch(tok){
+            case TOK_ASM_pic:
+            case TOK_ASM_nopic:
+            case TOK_ASM_relax:
+            case TOK_ASM_norelax:
+            case TOK_ASM_push:
+            case TOK_ASM_pop:
+                /* TODO: unimplemented */
+                next();
+                break;
+            case TOK_ASM_arch:
+                /* TODO: unimplemented, requires extra parsing */
+                tcc_error("unimp .option '.%s'", get_tok_str(tok, NULL));
+                break;
+            default:
+                tcc_error("unknown .option '.%s'", get_tok_str(tok, NULL));
+                break;
+        }
+        break;
 #endif
     default:
         tcc_error("unknown assembler directive '.%s'", get_tok_str(tok, NULL));
@@ -1014,7 +1037,9 @@ static void tcc_assemble_inline(TCCState *s1, char *str, int len, int global)
 {
     const int *saved_macro_ptr = macro_ptr;
     int dotid = set_idnum('.', IS_ID);
+#ifndef TCC_TARGET_RISCV64
     int dolid = set_idnum('$', 0);
+#endif
 
     tcc_open_bf(s1, ":asm:", len);
     memcpy(file->buffer, str, len);
@@ -1022,7 +1047,9 @@ static void tcc_assemble_inline(TCCState *s1, char *str, int len, int global)
     tcc_assemble_internal(s1, 0, global);
     tcc_close();
 
+#ifndef TCC_TARGET_RISCV64
     set_idnum('$', dolid);
+#endif
     set_idnum('.', dotid);
     macro_ptr = saved_macro_ptr;
 }

tcctok.h

@@ -202,7 +202,8 @@
 /* pragma */
      DEF(TOK_pack, "pack")
 #if !defined(TCC_TARGET_I386) && !defined(TCC_TARGET_X86_64) && \
-    !defined(TCC_TARGET_ARM) && !defined(TCC_TARGET_ARM64)
+    !defined(TCC_TARGET_ARM) && !defined(TCC_TARGET_ARM64) && \
+    !defined(TCC_TARGET_RISCV64)
      /* already defined for assembler */
      DEF(TOK_ASM_push, "push")
      DEF(TOK_ASM_pop, "pop")
@@ -401,6 +402,8 @@
  DEF_ASMDIR(code32)
 #elif defined(TCC_TARGET_X86_64)
  DEF_ASMDIR(code64)
+#elif defined(TCC_TARGET_RISCV64)
+ DEF_ASMDIR(option)
 #endif
  DEF_ASMDIR(short)
  DEF_ASMDIR(long)