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fixup! riscv: Implement large addend for global address 

Use `t1` instead of `t0` for the cases when `rr` is not set so `t0` is
used by default and this happens:

    lui t0, XXX
    add t0, t0, t0

Instead, now we do:

    lui t1, XXX
    add t0, t0, t1
This commit is contained in:
Ekaitz Zarraga 2024-04-28 00:13:01 +02:00
parent 8baadb3b55
commit 0aca861194
1 changed files with 2 additions and 2 deletions
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4
riscv64-gen.c
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@ -193,8 +193,8 @@ static int load_symofs(int r, SValue *sv, int forstore)
if (doload) {
EI(0x03, 3, rr, rr, 0); // ld RR, 0(RR)
if (large_addend) {
o(0x37 | (5 << 7) | ((0x800 + fc) & 0xfffff000)); //lui t0, high(fc)
ER(0x33, 0, rr, rr, 5, 0); // add RR, RR, t0
o(0x37 | (6 << 7) | ((0x800 + fc) & 0xfffff000)); //lui t1, high(fc)
ER(0x33, 0, rr, rr, 6, 0); // add RR, RR, t1
sv->c.i = fc << 20 >> 20;
}
}